Modern circuit designs often comprise a number of circuit blocks that are characterized and then re-used many times. The successful re-use of component circuit blocks thus hinges on the designer's ability to accurately characterize their timing and functionality. Static Timing Analysis (STA) is a design tool used to verify the timing behavior of a digital circuit design during one clock cycle, without the need to simulate the circuit. Complete transistor-level simulation of a circuit design is often too computationally expensive to use at all stages of the circuit design process, so digital circuit behavior is typically approximated.
The STA process calculates the approximate delay between a circuit's inputs and outputs. Such delay is one of the figures of merit for a circuit. A rising or falling voltage transition may be abstracted by a timing event, to approximate an actual circuit voltage waveform using only two parameters, the arrival time and slew rate. The arrival time of the transition may be based on the time that the voltage waveform reaches a selected reference voltage or trip point, such as a particular percentage of the supply voltage for example. The slew rate is the maximum rate of voltage change, which in STA may be estimated from the time the waveform takes to move from one given voltage to a second given voltage, where again the given voltages may be expressed as particular percentages of the supply voltage.
In advanced semiconductor fabrication processes, with design features now regularly at or below sixteen nanometers, real circuit component behavior is not always sufficiently straightforward that such analysis approximations are adequate. The approximation of the actual circuit waveform provided by the STA timing event for example may be too imprecise to verify the design's timing correctness. Even simple circuit blocks may prove challenging to characterize accurately with existing static timing methods in some circumstances.
A conceptually simple equivalent circuit block to be approximately characterized for STA may comprise merely a driver that drives a receiver, generally via an interconnect network. Drivers and receivers may comprise a variety of components, such as logic gates and their combinations for example. The interconnect network may be described by a network of resistors and capacitors (an RC network) that mimics the interconnect network behavior in a computationally inexpensive manner, or by a look-up table that provides descriptive information without requiring detailed simulation. Interconnect modeling has become well developed in the art. Focus therefore shifts to the role of the receiver in timing estimation. The electrical load the receiver places on a driver has become a significant part of the overall electrical load seen by the driver, and merits further modeling attention.
The receiver input capacitance becomes larger as a fraction of the total capacitance driven by a driver as design features are reduced in size. The electrical behavior of the receiver input capacitance also becomes less static and more dynamic at smaller geometries, meaning the time dependence and voltage dependence of the receiver becomes more complicated. The resulting nonlinear receiver capacitance is a leading cause of the resulting waveform anomalies that dominate delay calculation errors. Circuit timing analysis and verification accuracy therefore increasingly depend on the receiver load modeling accuracy.
The receiver load was traditionally modeled by a single “pin” capacitance obtained from a pre-characterized library. Prior art methods of adapting such capacitance models for more accuracy exist. One such method involves approximating the capacitance with an average value of a weighted sum of three individual values, with the weights found experimentally. The resulting transition time is then scaled by a “slew factor” computed from capacitance values at different voltage transition levels. This prior art method is simple and computationally fast, but is still inaccurate in some cases, and cannot capture physical phenomena well.
There are several important physical phenomena that are not currently well-modeled in digital circuit timing analysis, and more particularly in modeling receiver loads. One such phenomenon is the resistive shielding of the transistor gate capacitances, which results from the use of polysilicon transistor gates and contacts in advanced fabrication processes. Another phenomenon is the back-Miller effect, which is caused by coupling capacitance between a receiver's input and the first receiver output stage, particularly when the first receiver output stage is actively switching states. These effects tend to cause significant waveform anomalies that are not currently predicted accurately. As a result of the inadequacy of prior receiver load modeling efforts, the delays, transition rates, and other electrical measurements estimated by circuit timing tools may include significant errors.
The inventors have therefore developed an improved approach to more accurately modeling receiver loads in a circuit design, particularly for timing analysis of digital circuits.